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Experimental validation of a resilient electronic logic design with autonomous fault discrimination/masking

McWilliam, R.; Schiefer, P.; Purvis, A.

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Authors

R. McWilliam

P. Schiefer



Abstract

This paper presents the experimental validation of a novel fault-tolerant electronic logic design conducted by an automated mixed-signal fault injection procedure. The design under evaluation relies upon a novel redundant design strategy intended to provide fault discrimination and selective fault masking embedded within a functional CMOS NAND gate. The traditional logic layout is modified to include fault detection and reporting at an extremely fine-grained design level with 2x overhead as opposed to the traditional 4x overhead. The fault injection test bench procedure requires automated fault injection, programmable fault load conditions and combined analogue/digital domain verification. The device under test is implemented using discrete n- and p-FETs arranged as a modular test board together with automated fault injection and test lines. The fault response is measured and confirms the predicted intrinsic fault rate of 25% with a successful 100% masking of suck low-faults and precise identification of stuck-high via IDDQ trigger. The test procedure is shown to be extensible towards more complex logic unit designs and for evaluation of multiple simultaneous faults.

Citation

McWilliam, R., Schiefer, P., & Purvis, A. (2015). Experimental validation of a resilient electronic logic design with autonomous fault discrimination/masking. Procedia CIRP, 38, 265-270. https://doi.org/10.1016/j.procir.2015.08.027

Journal Article Type Article
Acceptance Date Aug 12, 2015
Publication Date Oct 27, 2015
Deposit Date Dec 11, 2015
Publicly Available Date Mar 28, 2024
Journal Procedia CIRP
Print ISSN 2212-8271
Publisher Elsevier
Peer Reviewed Peer Reviewed
Volume 38
Pages 265-270
DOI https://doi.org/10.1016/j.procir.2015.08.027
Keywords Self-healing technologies, FPGA, Hardware-in-loop, Fault injection, Fault-tolerance.

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