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Mapping statecharts to Verilog for hardware/software co-specification.

Qin, S. and Chin, W. N. (2003) 'Mapping statecharts to Verilog for hardware/software co-specification.', in FME 2003 : formal methods : International Symposium of Formal Methods Europe, 8-14 September 2003, Pisa, Italy: proceedings. Berlin: Springer , pp. 282-299. Lecture notes in computer science. (2805).

Abstract

Hardware-Software co-specification is a critical phase in co-design. Our co-specification process starts with a high level graphical description in Statecharts and ends with an equivalent parallel composition of hardware and software descriptions in Verilog. In this paper, we investigate the statecharts formalism by providing it a formal syntax and a compositional operational semantics. After that, we design a semantics-preserving mapping function to transform a Statecharts description into Verilog specification. We can combine this mapping with our previous formal partitioning process so as to form a more complete and automated co-specification process.

Item Type:Book chapter
Keywords:Statecharts, Verilog, Operational semantics, Homomorphism.
Full text:PDF - Accepted Version (426Kb)
Status:Peer-reviewed
Publisher Web site:http://dx.doi.org/10.1007/b13229
Publisher statement:The original publication is available at www.springerlink.com
Record Created:16 Nov 2009 16:50
Last Modified:29 Nov 2011 17:01

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