Mapping Statecharts to Verilog for Hardware/Software Co-Specification

Qin, S.; Chin, W.N.; Araki, K.; Gnesi, S.; Mandrioli, D.

doi:10.1007/978-3-540-45236-2_17

Mapping Statecharts to Verilog for Hardware/Software Co-Specification

Qin, S.; Chin, W.N.; Araki, K.; Gnesi, S.; Mandrioli, D.

Authors

S. Qin

W.N. Chin

K. Araki

S. Gnesi

D. Mandrioli

Abstract

Hardware-Software co-specification is a critical phase in co-design. Our co-specification process starts with a high level graphical description in Statecharts and ends with an equivalent parallel composition of hardware and software descriptions in Verilog. In this paper, we investigate the statecharts formalism by providing it a formal syntax and a compositional operational semantics. After that, we design a semantics-preserving mapping function to transform a Statecharts description into Verilog specification. We can combine this mapping with our previous formal partitioning process so as to form a more complete and automated co-specification process.

Citation

Qin, S., Chin, W., Araki, K., Gnesi, S., & Mandrioli, D. (2003). Mapping Statecharts to Verilog for Hardware/Software Co-Specification. In FME 2003 : formal methods : International Symposium of Formal Methods Europe, 8-14 September 2003, Pisa, Italy: proceedings (282-299). https://doi.org/10.1007/978-3-540-45236-2_17

Conference Name	Formal Methods : International Symposium of Formal Methods Europe (FME 2003)
Conference Location	Pisa, Italy
Start Date	Sep 8, 2003
End Date	Sep 14, 2003
Publication Date	Sep 25, 2003
Deposit Date	Nov 16, 2009
Publicly Available Date	Dec 10, 2009
Pages	282-299
Series Title	Lecture notes in computer science
Series Number	2805
Series ISSN	0302-9743,1611-3349
Book Title	FME 2003 : formal methods : International Symposium of Formal Methods Europe, 8-14 September 2003, Pisa, Italy: proceedings.
ISBN	9783540408284
DOI	https://doi.org/10.1007/978-3-540-45236-2_17
Keywords	Statecharts, Verilog, Operational semantics, Homomorphism.