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Realizing live sequence charts in SystemVerilog.

Wang, H. and Qin, S. and Sun, J. and Dong, J. S. (2007) 'Realizing live sequence charts in SystemVerilog.', in 1st Joint IEEE/IFIP Symposium on Theoretical Aspects of Software Engineering : June 6-8 2007, Shanghai ; proceedings. Los Alamitos, CA: IEEE , pp. 379-388.

Abstract

The design of an embedded control system starts with an investigation of properties and behaviors of the process evolving within its environment, and an analysis of the requirement for its safety performance. In early stages, system requirements are often specified as scenarios of behavior using sequence charts for different use cases. This specification must be precise, intuitive and expressive enough to capture different aspects of embedded control systems. As a rather rich and useful extension to the classical message sequence charts, live sequence charts (LSC), which provide a rich collection of constructs for specifying both possible and mandatory behaviors, are very suitable for designing an embedded control system. However, it is not a trivial task to realize a high-level design model in executable program codes effectively and correctly. This paper tackles the challenging task by providing a mapping algorithm to automatically synthesize SystemVerilog programs from given LSC specifications.

Item Type:Book chapter
Full text:PDF - Published Version (144Kb)
Status:Peer-reviewed
Publisher Web site:http://dx.doi.org/10.1109/TASE.2007.41
Publisher statement:© 2007 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.
Record Created:17 Nov 2009 12:20
Last Modified:08 Nov 2010 10:47

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