H. Wang
Realizing Live Sequence Charts in SystemVerilog
Wang, H.; Qin, S.; Sun, J.; Dong, J.S.
Authors
S. Qin
J. Sun
J.S. Dong
Abstract
The design of an embedded control system starts with an investigation of properties and behaviors of the process evolving within its environment, and an analysis of the requirement for its safety performance. In early stages, system requirements are often specified as scenarios of behavior using sequence charts for different use cases. This specification must be precise, intuitive and expressive enough to capture different aspects of embedded control systems. As a rather rich and useful extension to the classical message sequence charts, live sequence charts (LSC), which provide a rich collection of constructs for specifying both possible and mandatory behaviors, are very suitable for designing an embedded control system. However, it is not a trivial task to realize a high-level design model in executable program codes effectively and correctly. This paper tackles the challenging task by providing a mapping algorithm to automatically synthesize SystemVerilog programs from given LSC specifications.
Citation
Wang, H., Qin, S., Sun, J., & Dong, J. (2007). Realizing Live Sequence Charts in SystemVerilog. In 1st Joint IEEE/IFIP Symposium on Theoretical Aspects of Software Engineering : June 6-8 2007, Shanghai ; proceedings (379-388). https://doi.org/10.1109/tase.2007.41
Conference Name | First Joint IEEE/IFIP Symposium on Theoretical Aspects of Software Engineering (TASE 2007) |
---|---|
Conference Location | Shanghai, China |
Start Date | Jun 6, 2007 |
End Date | Jun 8, 2007 |
Publication Date | Jun 1, 2007 |
Deposit Date | Nov 17, 2009 |
Publicly Available Date | Nov 8, 2010 |
Publisher | Institute of Electrical and Electronics Engineers |
Pages | 379-388 |
Book Title | 1st Joint IEEE/IFIP Symposium on Theoretical Aspects of Software Engineering : June 6-8 2007, Shanghai ; proceedings. |
DOI | https://doi.org/10.1109/tase.2007.41 |
Files
Published Conference Proceeding
(147 Kb)
PDF
Copyright Statement
© 2007 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.
You might also like
PTSC: probability, time and shared-variable concurrency
(2009)
Journal Article
Memory Usage Verification Using Hip/Sleek
(2009)
Conference Proceeding
An Interval-based Inference of Variant Parametric Types
(2009)
Conference Proceeding
A Heap Model for Java Bytecode to Support Separation Logic
(2008)
Conference Proceeding
Downloadable Citations
About Durham Research Online (DRO)
Administrator e-mail: dro.admin@durham.ac.uk
This application uses the following open-source libraries:
SheetJS Community Edition
Apache License Version 2.0 (http://www.apache.org/licenses/)
PDF.js
Apache License Version 2.0 (http://www.apache.org/licenses/)
Font Awesome
SIL OFL 1.1 (http://scripts.sil.org/OFL)
MIT License (http://opensource.org/licenses/mit-license.html)
CC BY 3.0 ( http://creativecommons.org/licenses/by/3.0/)
Powered by Worktribe © 2024
Advanced Search