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An automatic mapping from Statecharts to Verilog.

Viet-Anh, T. V. and Qin, S. and Chin, W.-N. (2004) 'An automatic mapping from Statecharts to Verilog.', in Theoretical computing : 1st International Colloquium, ICTAC 2004, 20-24 September 2004, Guiyang, China ; revised selected papers. Berlin: Springer , pp. 187-203. Lecture notes in computer science. (3407).


Statecharts is a visual formalism suitable for high-level system specification, while Verilog is a hardware description language that can be used for both behavioural and structural specification of (hardware) systems. This paper implements a semantics-preserving mapping from Graphical Statecharts to Verilog programs, which, to the best of our knowledge, is the first algorithm to bridge the gap between Statecharts and Verilog, and can be embedded into the hardware/software co-specification process [19] as a front-end.

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Record Created:17 Nov 2009 13:05
Last Modified:31 Mar 2015 13:00

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