An Automatic Mapping from Statecharts to Verilog

Viet-Anh, T.V.; Qin, S.; Chin, W.N.; Liu, Z.; Araki, K.

doi:10.1007/978-3-540-31862-0_15

An Automatic Mapping from Statecharts to Verilog

Viet-Anh, T.V.; Qin, S.; Chin, W.N.; Liu, Z.; Araki, K.

Authors

T.V. Viet-Anh

S. Qin

W.N. Chin

Z. Liu

K. Araki

Abstract

Statecharts is a visual formalism suitable for high-level system specification, while Verilog is a hardware description language that can be used for both behavioural and structural specification of (hardware) systems. This paper implements a semantics-preserving mapping from Graphical Statecharts to Verilog programs, which, to the best of our knowledge, is the first algorithm to bridge the gap between Statecharts and Verilog, and can be embedded into the hardware/software co-specification process [19] as a front-end.

Citation

Viet-Anh, T., Qin, S., Chin, W., Liu, Z., & Araki, K. (2004). An Automatic Mapping from Statecharts to Verilog. In Theoretical computing : 1st International Colloquium, ICTAC 2004, 20-24 September 2004, Guiyang, China ; revised selected papers (187-203). https://doi.org/10.1007/978-3-540-31862-0_15

Conference Name	First International Colloquium on Theoretical Aspects of Computing (ICTAC 2004)
Conference Location	Guiyang, China
Start Date	Sep 20, 2004
End Date	Sep 24, 2004
Publication Date	Sep 24, 2004
Deposit Date	Nov 17, 2009
Publicly Available Date	Dec 10, 2009
Pages	187-203
Series Title	Lecture notes in computer science
Series Number	3407
Series ISSN	0302-9743,1611-3349
Book Title	Theoretical computing : 1st International Colloquium, ICTAC 2004, 20-24 September 2004, Guiyang, China ; revised selected papers.
ISBN	9783540253044
DOI	https://doi.org/10.1007/978-3-540-31862-0_15