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Hardware/software partitioning in Verilog.

Qin, S. and He, J. and Qiu, Z. and Zhang, N. (2002) 'Hardware/software partitioning in Verilog.', in Formal methods and software engineering : 4th International Conference on Formal Engineering Methods, ICFEM 2002, 21-25 October 2002, Shanghai, China ; proceedings. Berlin: Springer, pp. 168-179. Lecture notes in computer science. (2495).

Abstract

We propose in this paper an algebraic approach to hardware/software partitioning in Verilog HDL. We explore a collection of algebraic laws for Verilog programs, from which we design a set of syntax-based algebraic rules to conduct hardware/software partitioning. The co-specification language and the target hardware and software description languages are specific subsets of Verilog, which brings forth our successful verification for the correctness of the partitioning process by algebra of Verilog. Facilitated by Verilog’s rich features, we have also successfully studied hw/sw partitioning for environment-driven systems.

Item Type:Book chapter
Keywords:Verilog, Algebraic laws, Hardware/software co-design, Hardware/software partitioning.
Full text:PDF (Copyright agreement prohibits open access to the full-text) - Accepted Version
Publisher-imposed embargo
(6588Kb)
Status:Peer-reviewed
Publisher Web site:http://dx.doi.org/10.1007/3-540-36103-0_19
Record Created:20 Nov 2009 17:05
Last Modified:09 Oct 2014 13:32

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