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Performance predictions for a silicon velocity modulation transistor.

Crow, G.C. and Abram, R.A. (1999) 'Performance predictions for a silicon velocity modulation transistor.', Journal of applied physics., 85 (2). pp. 1196-1202.

Abstract

A Monte Carlo simulation has been devised and used to model submicron Si velocity modulation transistors with the intention of designing a picosecond switch. The simulated devices have nominal top and back gate lengths of 0.1 μm, and the conduction channels have similar thickness. Mobility modulation has so far been achieved by heavily compensated doping and interface roughness at one side of the channel. The simulated devices have a high intrinsic speed; simulations performed for T = 77 K suggest that current can be switched between the low and high mobility regions of the channel within 1.5 ps. However, in unstrained Si devices the main obstacle to practical device operation is the rather small current modulation factor (the ratio of the steady drain currents for the device operating in the high and low mobility regimes), which decreases towards unity with increasing drain–source bias. Such a device should work best for small electric fields along the channel ( ∼ 105 V m−1), the regime where impurity scattering has its greatest influence on the electron mobility.

Item Type:Article
Full text:PDF - Published Version (313Kb)
Status:Peer-reviewed
Publisher Web site:http://dx.doi.org/10.1063/1.369245
Publisher statement:Copyright (1999) American Institute of Physics. This article may be downloaded for personal use only. Any other use requires prior permission of the author and the American Institute of Physics. The following article appeared in Crow, G.C. and Abram, R.A. (1999) 'Performance predictions for a silicon velocity modulation transistor.', Journal of applied physics., 85 (2). pp. 1196-1202 and may be found at http://dx.doi.org/10.1063/1.369245
Record Created:07 Dec 2010 13:05
Last Modified:07 Dec 2010 14:07

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